1. Field of the Invention
This invention relates to the manufacture of semiconductor substrates and, more particularly, to a method for determining the best focus during a photolithography imaging procedure and to a method for adjusting the focus value a wafer is exposed with by monitoring focus on an integrated wafer during the photolithography imaging procedure of the manufacturing process by calculating the amount of any focus drift away from a predetermined best focus and thus determining what correction to apply to return the process to best focus.
2. Description of Related Art
The manufacture of semiconductor substrates such as wafers and chips involve the use of high-resolution lithography systems. In such systems, the patterned mask (i.e., reticle) is illuminated with radiation (e.g., laser radiation or radiation from an arc lamp) that passes through the illumination system and achieves high-degree illumination uniformity over the illuminated portion of the mask. A portion of the radiation that passes through the mask is collected by a projection lens, which has an image field of a given size. The projection lens images the mask pattern onto an image-bearing substrate or workpiece such as a wafer. The workpiece resides on a workpiece stage that moves the workpiece relative to the projection lens so that the mask pattern is repeatedly formed on the workpiece over multiple “exposure fields.” An “exposure field” is defined as the mask pattern which is formed on the wafer during the step-and-scan process of the mask pattern.
Lithography systems include an alignment system that precisely aligns the workpiece with respect to the projected image of the mask thereby allowing the mask to be exposed over a select region of the workpiece. Two types of lithography systems are typically used in manufacturing. One system is the step-and-repeat system, or “steppers” and the other is the step-and-scan system, or “scanner.” With steppers, each exposure field on the workpiece is exposed with a single static exposure. With scanners, the workpiece is exposed by synchronously scanning the workpiece and the mask across the lens image field. An exemplary scanning lithography system and method is described in U.S. Pat. No. 5,281,996, which is incorporated herein by reference. The following description will be mainly directed to the step-and-scan system although it will be understood by those skilled in the art that the invention is applicable to any type imaging system.
As is well known, in a typical photolithographic process, a thin layer of a photosensitive material or photoresist is deposited over a semiconductor wafer. Each wafer typically has many chips thereon. During the photolithography process, illumination such as ultra-violet light is illuminated through a lens system and a photolithographic mask or reticle to a chip on the semiconductor wafer. The reticle has a particular device pattern and the pattern is exposed over a portion of the chip by the illumination to create exposed and unexposed regions on the chip. These exposed or unexposed regions are then washed away to define circuit elements on the chip. This photolithography process is repeated many times on different layers of the semiconductor processor, with intermediate processing steps, to define many circuit elements on the chips on the wafer.
Typically, a reticle is made from a transparent plate that has an opaque pattern on it which defines the pattern. The plate is often made of glass, quartz, or the like and the opaque region typically includes a layer of chrome. The device exposure region generally has a square or rectangular shape and is positioned in the center of the reticle. The device exposure region includes transparent portions and opaque portions defining a device pattern. The transparent portions in the device exposure region allow illumination from a light source to travel through them and reach the wafer. On the other hand, the opaque regions of the device region block the light and the light does not reach the wafer.
FIG. 5 shows a typical prior art reticle 80 having a square device region 82 surrounded by an opaque chrome region 84. For the sake of simplicity, a device pattern 88 in the device region is not illustrated in detail in the figure. There is a kerf region 86 at the periphery of the device region 82 between the device region 82 and opaque chrome region 84. The kerf region 86 typically contains structures used to align to prior levels and usually includes test structures to verify the performance of a photolithographic and/or other processes. For example, the kerf region may include alignment marks to allow for accurate reticle alignment and marks to measure the resolution of the device pattern during the photolithographic process.
Lithographic imaging is highly dependent on substrate uniformity. A lithographic process can tolerate a small range of topography variation through the “depth of focus” inherent in the process capability. However, unanticipated topography variation on the substrate is a known problem for lithography processes and can result in a faulty imaging process and a rejection of the imaged workpiece.
Modern exposure systems such as the step-and-scan exposure system utilize an optical leveling system to control the height (focus) of the scanning slit above the wafer. The exposure tool can adjust to fluctuations in step-height by a set of simple linear motions. The problem arises when major step-height changes or differences in pattern density occur across the reticle field as shown in FIG. 2A. Region A has an isolated via 58 and region B has a dense via field 60. Even sophisticated leveling systems are faced with a conflict on where to place the imaging focal plane relative to the pattern density and, in general, trade-offs are made in some form of minimizing the average focus displacement across the imaging field.
Focus error is typically quantified as an offset error in the location of the wafer in the Z-axis relative to a perfectly focused image plane. This focus offset or defocus (measured, for example, in nanometers) has a positive or negative Z-axis displacement with respect to ideal focal plane, along with a magnitude representative of the distance by which surface is offset from the ideal focal plane. By determining the direction of misfocus (i.e., the positive or negative Z-axis translation of the wafer), along with a displacement value, accurate adjustment of wafer back to proper focus can be accomplished. For example, through manual or automated adjustment of the position controller controlling the X, Y, Z location of the wafer within the wafer scanner the wafer could be repositioned to reduce focus error so as to improve system resolution.
In operation, at each step, or field, the scanner performs a focusing operation, typically by moving the wafer in the z-direction to match the wafer surface with the optimum image plane of the optical system. To perform the focusing operation, certain focus data, specifically, the position of the wafer surface in the z-direction, is measured and the position of the wafer in the z-direction is servo-controlled to modify the detected focus shift amount.
To obtain best focus, the critical dimension (CD) is plotted as a function of focus. The difference in CD from one focus step to the next becomes less and less as the best focus is approached. Under ideal conditions, the best focus is the point at which variation in the CD between successive focus steps is at a minimum. In another expression of this method, a polynomial curve can be used to fit the CD to focus, and the best focus will be at a point where the slope of the polynomial curve is zero. Both “concave up” and “concave down” responses are possible, depending on the feature type, photoresist chemistry and processing, and therefore a minima or maxima of the polynomial curve is possible. In either case, the best focus is at the point where the slope of the polynomial curve is zero. Various other statistical techniques can be used to calculate the best focus.
One of the more widely used techniques for determination of best focus is the so-called “Bossung plot” method. When a CD metrology tool such as a CD-SEM or scatterometer measures CD of a selected feature printed through a range of focus, the resulting trend is usually polynomial. Fitting a polynomial curve to the CD trend and determining where the slope of the curve is zero identifies best focus. These curves are known as Bossung plots. One advantage to the Bossung method is that the actual CD of the process is quantified in addition to the best focus condition. However, the fact that this technique for determining best focus requires a wafer with varying focus to be printed and measured, prevents it from being used to monitor a tools focus drift on a lot to lot basis. Specifically, while the original determination of best focus determination is accurate for the specific wafer which it was determined on, a best focus determined by a wafer shot with varying focus steps the next day, or even later the same day, could be different due to exposure tool focus drift. However, the method requires a wafer be printed and measured with varying focus, which makes it a non-ideal method to determine best focus and difficult to implement in an automated manner. This is because of the cost associated with having to throw out chips that are printed not at best focus due to reliability concerns. Even if the wafers with varying focus were reworked there is still the cost of the exposure and metrology tool time.
U.S. Pat. No. 6,081,614 to Yamada et al. relates to a surface position detecting method applicable to a slit-scan type or scanning exposure type exposure apparatus, for continuously detecting the position or tilt of the surface of a wafer with respect to the direction of an optical axis of a projection optical system. As discussed therein, the focusing of a mask image in these apparatuses continuously performs corrective drive for auto-focusing and auto-leveling during the scanning exposure process. A level and surface positioning detecting mechanism uses an oblique projection optical system wherein light is projected to the surface of a wafer obliquely from above and wherein reflection light from the photosensitive substrate is detected as a positional deviation upon a sensor. From the measured values of level during the scan, a corrective drive amount is made to the level (height) and tilt of the wafer as the measurement position passes the exposure slit region. The disclosure of this patent is incorporated herein by reference.
The Yamada et al. patent improves the wafer positioning by measuring beforehand errors to be produced with respect to the level detection points due to a difference in pattern structure among the level detection points disposed along the scan direction. The measurement error with respect to each level detection point is then used to correct the position of the wafer using the surface position detecting system.
Thus, there still exists a need for a methodology to easily determine the best focus and to monitor focus during the lithography step in the manufacture of semiconductor wafers to ensure that each wafer is exposed with as close to best focus as possible.
As noted above, the subject patent application is applicable to any such leveling system.